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| TECHNICAL DATA CMOS timer with RAM and I2C-bus control. KKA8583N KKA8583N is a timer with RAM and I2C-bus control. Designed for use in appliances having I2C-bus as clock/calendar/timer/alarm/events counter for turning on functions of the appliance at preset time or upon completion of an event. To be used in audio and appliances. - I2C- bus interface operating supply voltage: 2.5 V to 6 V; - Clock operating supply voltage ( 0/70): 1.0 V to 6 V; 50 ; - Operating current (at fSCL = 0Hz): - Clock function with four year calendar; - 24 or 12 hour format; - 32.768 kHz or 50Hz time base; - Serial bus (I2C); - Automatic word address in crementation; - Programmable alarm, timer and interrupt function; - Operating temperature range: -20 to +70 . - Features: TA = -20 T 70 C Table1 - PIN ASSIGNMENT OSCI OSCO A0 GND SDA SCL INT Vcc Pin 1 2 3 4 5 6 7 8 Generator input, 50Hz or occurrences Generator output Address input GND Data for I2C-bus Clock pulses for I2C-bus Open-drain interrupt output Supply voltage Pinning diagram OSCI OSCO A0 GND 1 2 3 4 8 7 6 5 Vcc INT SCL SDA Fig.1 1 KKA8583 Block diagram KKA8583N KKA8583N OSCI OSCO INT VCC GND A0 SCL SDA I2C-bus interface Address register Power-on reset KKA8583 OSCILLATOR 32.768kHz Divider 1:256 or 100:128 100Hz Control logic Control/status Hundredth of a second seconds minutes hours Year/date Weekday/months timer Alarm control Alarm regisers or RAM RAM (2408) 00 01 07 08 0F FF Fig. 2. 2 KKA8583 Table 2 - Recommend-operating conditions Parameter Symbol Unit Supply voltage, Vcc, V operating clock Low input voltage, Vil, V High input voltage, Vih, V Operating ambient temperature, Tamb, C Input frequency, fI, MHz Limits Not more 2.5 1.0 0 0.7*Vcc -20 1 Not less 6.0 6.0 0.3*Vcc Vcc +70 Only for event mode Note Tamb=0/+70C Table3 - Absolute maximum rating Parameter Limits Note Symbol Unit Not more Not less Supply voltage, Vcc, V -0.8 7,0 Input voltage for all inputs, VI, V -0.8 Vcc+0.8 Note1 Max output current, Io, mA 10 Max input current, II, mA 10 Current through inputs 04 or 08, IDD, 50 ISS, m Power dissipation on package, TOT, 300 mW Power dissipation on output , , mW 50 -65 +150 Storage temperature, Tstg, Notes: 1. If voltage on diode is higher than VCC or lower than GND, the current will flow, the current should be not more than 0.5mA. 3 KKA8583 Table 4 - Electrical parameters. Parameter, Symbol unit Supply Supply current ,I, A Supply current for clock, I0, A Data storage supply current, ICCR, A I C-bus enable level, VPOR, V Input/output SDA Low output current, IOL, mA Input leakage current, |II|, A 2 Limit Not less Not more 200 50 10 5 2 2.3 Testing conditions Temperature, C Vcc=6V T=-20 FSCL= 100kHz +25 +70 Vcc=5V Vcc=1V Note 1 VCC= 1V VCC= 1V Note 2 1.5 3 1 Vcc= 6 V Vol= 0.4 V Vcc= 6 V VIL= 0 V VIH= 6 V VI=0 V Vcc= 6 V VIL= 0 V VIH= 6 V Vcc=6.0 V VOL=0,4 V Vcc= 6 V VIL= 0 V VIH= 6 V SCL, SDA Input capacity, I,pF Inputs A0, OSCI Input leakage current, |II|, nA Output INT Output low current, IOL, mA Input leakage current, |II|, A 3 7 250 1 Notes: 1. For event mode or 50Hz only. 2. The I2C-bus logic is disabled if VCC < VPOR. 4 KKA8583 KKA8583N contains 2568 RAM 8-bit. The word address register which is incremented automatically, built-in 32.768 kHz oscillator circuit, frequency divider, interface of two line bi-directional serial I2C-bus and power-on reset circuit. The first 8 bits of the RAM (addresses 00/07) are designated ass addressable 8-bit parallel registers. The first register (address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory address 08/0F may be used as free RAM locations or may be programmed as alarm registers. The following modes can be selected by setting the control/status register: Clock mode from 32.768 kHz; Clock mode from 50 Hz; Event counter mode. In the clock mode hundredths of a second, seconds, minutes, hours, date, month (four-year calendar) and a weekday are stored in a BCD format. The timer register stores up to 99 days. The event counter mode is used for counting pulses applied to the oscillator input (OSCO left opencircuit). In BCD format the event counter stores up to 6 digits. By setting the alarm enabling bit of the control/status register the alarm control register (address 08) is activated. By setting the alarm control register the following may be programmed: Dated alarm; Weekday alarm; Daily alarm; Timer alarm. In the clock mode the timer register (address 07) may be programmed to count hundredths of a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed. Whenever an alarm event occurs the alarm flag of the control/status register is set, and an overflow condition of the timer will set the timer flag. The open drain interrupt output is switched on (active LOW) when the alarm or timer flag is set. The flags remain set until directly reset by a write operation to register (00 address). When the alarm is disabled the remaining alarm registers (addresses 09/0F) may be used as free RAM. In the clock modes 24hr or 12hr format can be selected by setting the most significant bit of the hours counter register. 5 KKA8583 Register arrangement. Control/status Hundredth of second seconds minutes hours Year/date Weekday/month timer Alarm control Hundredth of second Alarm seconds Alarm minutes Alarm hours Alarm date Alarm month Alarm timer Free RAM Clock modes Fig. 3. Control/status D1 D3 D5 free free free timer 1 timer 0 Alarm control alarm D1 alarm D0 D3 D2 D5 D4 free free free Alarm timer Free RAM Event counter D0 D2 D4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Table 5. - Cycle length of the time counters, clock modes. Unit Hundredths of a second Seconds Minutes Hours (24 h) Hours (12 h) Date Counting cycle 00 / 99 00 / 59 00 / 59 00 / 23 12, 01/11, 12, 01/11 01/31 01/30 01/29 01/28 01/21 0/3 0/6 00/99 Carry to next unit 99 to 00 59 to 00 59 to 00 23 to 00 11 to 12 31 to 01 30 to 01 29 to 01 28 to 01 12 to 01 3 to 0 6 to 0 No carry Contents of the month counter 1, 3, 5, 7, 8, 10, 12 4, 6, 9, 11 2, year = 0 2, year = 1, 2, 3 Months Year Weekdays Timer 6 KKA8583 The year and date are packed into memory location 05. The weekdays and months are packed into memory location 06. When reading these memory locations the year and weekdays may be masked out when the mask flag of the control/status register is set. This allows the user to read the date and month counters only. In the event counter mode data are stored in BCD format. D5 is the most significant and do the least significant digit. In this mode the internal divider is by-passed. By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated. All functions of the alarm, timer and interrupt output are controlled by the contents of the alarm control register. All alarm registers are arranged starting from 08 address. An alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignored the month and date bits. When a weekday alarm is selected, for comparison a bit will be selected from the alarm register per the weekday (address OE) corresponding to the weekday on which the alarm is activated. Interrupt output (with open drain) is programmed by setting the alarm control register. It enables (active LOW) when the alarm flag or timer flag are set. The voltage level in ON state (HIGH) on the interrupt output may be more than the supply voltage. A 32.768 kHz quartz crystal may be connected to OSCI (pin 1) and OSCO (pin 2). A trimmer capacitor between OSCI and supply is used for tuning the oscillator. A 100 Hz clock signal is derived from the quartz oscillator for the clock counters. In the 50Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high impedance state. This allows the user to feed the 50Hz reference frequency or an external high speed event signal into the input OSCI. When power-up occurs the I2C-bus interface, the control/status register and all clock counters are reset. After the device starts time-keeping in the 32.768kHz clock mode with the 24hr format on the square wave appears at the interrupt output pin (starts HIGH). This may be abolished by setting the alarm enable bit in the control/status register. The 2nd signal of interface of I2C-bus is generated as soon as the supply voltage below the reset level of I2C-bus interface. This reset signal does not affect the registers of hour counter and control/status register. It the recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction. I2C-bus is a bi-directional, two-line communication between different ICs and modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines shall be connected to a positive supply via a resistor since in IC these outputs have "open drain". Data transfer may be initiated only when the bus is not busy. 7 KKA8583 One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. . Bit transfer SDA SCL Data valid change of data allowed Fig. 4. Both SDA and SCL lines remain HIGH when the bus is not busy. The HIGH-to-LOW transition of the data line, while the clock is High is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (). Definition of start and stop conditions. SDA SCL S Fig. 5. A device generating a message is a "transmitter" a device receiving a message is a "receiver". The device that controls the message is the "master", and the devices which are controlled by the master are "slaves". The number of data bytes transferred between the start and stop conditions from the transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. P 8 KKA8583 Acknowledgment on the I2-bus. Start condition SCL from master data output by receiver data output by transmitter S Fig. 6. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception o each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse. A master receiver must signal an end of date to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Before any date is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. Master transmits to slave receiver (WRITE) mode. acknowledgement from slave S Slave address 0 R/W n bytes auto increment memory word address Fig. 7. acknowledgement from slave data acknowledgement from slave 1 2 8 Clock pulse for acknowledgement 9 Word address 9 KKA8583 Master reads after setting word address (write word address; READ data). acknowledgement from slave S Slave address 0 R/W At this moment master-transmitter becomes master-receiver and KKA8583N slave-receiver becomes slave-transmitter. acknowledgement from master Data n byte auto increment word address Data last byte auto increment word address Fig. 8. Master reads slave immediately after first byte (READ mode). acknowledgement from slave S Slave address 1 R/W Data n bytes auto increment word address Fig. 9. acknowledgement from master Data last byte auto increment word address no acknowledgement from master 1 no acknowledgement from master 1 acknowledgement from slave S Slave address acknowledgement from slave 1 R/W Word address 10 KKA8583 Application circuit VCC Master VCC 0 SCL OSCI KKA8583N SDA OSCO GND SDA transmitter SCL VCC VCC VCC 0 SCL OSCI KKA8583N SDA OSCO GND VCC R R Fig.10 11 KKA8583 Table 6 - Symbols Symbol S P A Description START condition STOP condition Bit acknowledge KKA8583N address 1 0 1 0 0 0 0 R/W Group1 Fig. 11. Group 2 N SUFFIX PLASTIC DIP (MS - 001BA) A 8 5 B 1 4 Dimension, mm Symbol A B MIN 8.51 6.1 MAX 10.16 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78 F L C D C -T- SEATING N G D 0.25 (0.010) M T K PLANE F G M H J H J K L M N NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. 12 |
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